1. Field of the Invention
This invention relates to a common memory data switch for routing data signals.
2. Description of Related Art
A primary goal in a digital communications network is to connect data sources with desired data destinations. To accomplish this goal, a signal travelling from a source generally must be routed through one or more network switches in order to reach a particular destination. One scheme for realising such network communications involves the creation of digital information cells in the network, each cell comprising a fixed number of bytes comprising a block of data and a header which provides an indication of the destination for the cell. The header of a cell is used by the network switches to appropriately route the cell. Such cells may propagate asynchronously in the network leading to the designation of "asynchronous transfer mode" or ATM for this scheme.
One type of network switch which may be used in an ATM network is a common memory switch. For example, U.S Pat. No. 4,603,416 to Servel issued Jul. 29, 1986 discloses a common memory data switch for routing ATM cells. In Servel, the destination specified by a particular header is dependent upon the particular input channel, that is, a header is not unique between channels. Thus, an indication of the input channel, along with the header, is necessary to completely specify the destination for the cell and, hence, the output channel to which the cell is to be routed in any particular switch.
The switch of Servel has an input circuit coupled to each input channel which collects a serial cell (which may be either an information bearing cell or an idle cell) propagating along the channel. A multiplexer cyclically scans consecutive input circuits to port collected cells from consecutive circuits to a serial to parallel converter. Accordingly, during one cycle of the multiplexer, the converter outputs parallel cells from each input channel in consecutive order. The order of the cells leaving the converter during one cycle of operation thus indicates the input channel number of the cell. This implicit input channel number and the header of the cell are applied to a look-up table which returns a destination channel number and a new header for the cell. The new header is married to the cell and the derived destination channel number is applied to the write enable inputs of a plurality of queues, one of which is assigned to each output channel, in order to write enable the queue assigned to the output channel represented by the destination channel number. The output of a cyclical local clock forms the data input of the queues and, through a multiplexer, also forms the write address input of a buffer memory whose data input is coupled to the output of the series to parallel converter. Consequently, the address of any cell stored in the buffer memory is also stored in a queue assigned to the output channel for which the cell is destined.
The queues assigned to the output channels are cyclically scanned so that they sequentially transmit read addresses to the buffer memory. This causes the buffer memory to output cells intended for consecutive output channels to a parallel to serial converter which ports the cell to the intended output channel by virtue of the position of the cell in the cycle.
While Servel discloses a system for the routing of ATM signals, his system will not handle signals having a different format. Thus, Servel cannot handle synchronous transfer mode (STM) signals. By way of explanation, STM signals are synchronous signals of a fixed length (generally one byte long) having no headers. That is, STM signals do not include leading bytes indicating their destination; instead the synchronous nature of these signals are exploited to permit proper routing of such signals, as will be explained hereinafter. The subject invention seeks to overcome drawbacks present in known data switching systems.